The workshop will take place on Monday, September 5, 2016 at the SISPAD conference location (Le Meridien Grand Hotel).
The workshop fee is 60 EUR and includes workshop proceedings (printed handout of the slides), lunch, and coffee breaks.
To register for the workshop choose the workshop option "WS3" in the online registration form or just send an e-mail to email@example.com. You can register for the workshop independent of the registration for the conference.
Compact models provide a bridge between the physical simulation of the process steps used for device fabrication and the device performance on one side and the design of the chips based on these technologies on the other side. Hierarchical simulation systems are needed to describe and predict the impact of the fabrication processes on the chips designed. Such tools are both mandatory for Design Technology Co-Optimization (DTCO) and an important subject of current research. The challenge becomes even more severe when the impact of inevitable systematic and stochastic process variations must be assessed and minimized. Therefore, Variability-Aware Design Technology Co-Optimization is an important approach to optimize the yield for chips which are fabricated in aggressively scaled semiconductor technologies, affected by process variations.
The workshop addresses this wide area by presentations from related European projects, semiconductor companies faced with this challenge, software houses which can provide parts of the solution, and research institutes active in this area.
The workshop is organized by A. Asenov (Glasgow University) and J. Lorenz (Fraunhofer IISB) in cooperation with the projects SUPERTHEME, MoRV and SUPERAID7, funded by the EC within its FP7 and Horizon 2020 programs, respectively.
|9:30||Welcome and Orientation||J. Lorenz (Fraunhofer IISB)|
|9:45||Challenges and Prospects for Variability-Aware DTCO||A. Asenov (Glasgow University)|
|Session on Related European Projects (EP)|
|10:00||EP 1: Outline and Selected Results of the EC FP7 Project SUPERTHEME||J. Lorenz (Fraunhofer IISB)|
|10:30||EP 2: Physical Models for Variation-Aware Device Simulation||M. Nedjalkov (TU Wien)|
|Session on Related European Projects (cont.)|
|11:30||EP 3: Variability-Aware Compact Models||C. Millar (GSS)|
|12:00||EP 4: Modeling of Variability under Reliability: The MORV Project||D. Helms (OFFIS)|
|12:30||EP 5: Variability from Equipment to Circuit: The Horizon2020 Project SUPERAID7||J. Lorenz (Fraunhofer IISB)|
|14:00||Variation Source Identification and Control with Behavioral Modeling||W. Clark (Coventor)|
|14:30||Pathfinding through DTCO: PPA Evaluation of 5 nm Technology||P. Asenov / V. Moroz (Synopsys)|
|15:00||Panel Discussion on Challenges and Solutions of Variation-Aware DTCO|